 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| ? 2011 microchip technology inc. ds39972b-page 1 pic18fxxk80 family 1.0 device overview this document includes the programming specifications for the following devices: 2.0 programming overview the pic18fxxk80 family of devices can be programmed using the in-circuit serial programming? (icsp?) method. this programming specification applies to the pic18fxxk80 family of devices in all package types. 2.1 hardware requirements when programming with the icsp, the pic18fxxk80 family requires two programmable power supplies; one for v dd and one for mclr /v pp /re3. both supplies should have a minimum resolution of 0.25v. refer to section 6.0 ?ac/dc characteristics timing requirements for program/verify test mode? for additional hardware parameters. 2.1.1 low-voltage icsp? programming in low-voltage icsp mode, the pic18fxxk80 family can be programmed using a v dd source in the operat- ing range. the mclr /v pp /re3 pin does not have to be brought to a different voltage, but can instead, be left at the normal operating voltage. refer to section 6.0 ?ac/dc characteristics timing requirements for program/verify test mode? for additional hardware parameters. 2.2 pin diagrams the pin diagrams for the pic18fxxk80 family are shown in figure 2-1 and figure 2-2 . table 2-1: pin descriptions (during programming): pic18fxxk80 family ? pic18f25k80 ? pic18f26k80 ? pic18lf25k80 ? pic18lf26k80 ? pic18f45k80 ? pic18f46k80 ? pic18lf45k80 ? pic18lf46k80 ? pic18f65k80 ? pic18f66k80 ? PIC18LF65K80 ? pic18lf66k80 pin name during programming pin name pin type pin description mclr /v pp /re3 v pp p programming enable v dd (1) v dd p power supply v ss (1) v ss p ground av dd av dd p analog power supply av ss av ss p analog ground rb6 pgc i serial clock rb7 pgd i/o serial data v ddcore / v cap v ddcore p regulated power supply for microcontroller core v cap i filter capacitor for on-chip voltage regulator legend: i = input, o = output, p = power note 1: all power supply (v dd ) and ground (v ss ) pins must be connected. flash microcontroller pr ogramming specification
pic18fxxk80 family ds39972b-page 2 ? 2011 microchip technology inc. figure 2-1: pic18fxxk80 family pin diagrams 28-pin qfn ? pic18f25k80 ? pic18f26k80 the following devices are included in 28-pin qfn parts: ra1 rb3 ra2 v ddcore /v cap ra5 ra7 1 2 3 4 7 5 6 21 20 19 18 15 17 16 28 27 26 25 24 23 22 8 9 10 11 12 13 14 ra0 mclr /v pp /re3 rb7/pgd rc0 rc1 rc2 rc3 ra3 v ss ra6 rb2 rb1 rb0 v dd v ss rc7 rc4 rc5 rc6 rb6/pgc rb5 rb4 pic18f2xk80 ? pic18lf25k80 ? pic18lf26k80 ? 2011 microchip technology inc. ds39972b-page 3 pic18fxxk80 family figure 2-2: pic18f8xkx x family pin diagrams 28-pin pdip/soic/ssop the following devices are included in 28-pin pdip/soic/ssop parts: ra1 rb3 ra2 v ddcore /v cap ra5 ra7 rb7/pgd 1 2 3 4 7 5 6 8 9 10 11 14 12 13 19 18 15 17 16 24 23 20 22 21 25 26 27 28 ra3 v ss ra6 rb2 rb1 rb0 v dd v ss rc7 rc4 rc5 rc6 rb6/pgc rb5 rb4 mclr /v pp /re3 ra0 rc0 rc1 rc2 rc3 pic18f2xk80 ? pic18f25k80 ? pic18f26k80 ? pic18lf25k80 ? pic18lf26k80 pic18fxxk80 family ds39972b-page 4 ? 2011 microchip technology inc. figure 2-3: pic18f8xkx x family pin diagrams 40-pin pdip the following devices are included in 40-pin pdip parts: ? pic18f45k80 ? pic18f46k80 1 2 3 4 7 5 6 8 9 10 11 14 12 13 19 18 15 17 16 24 23 20 22 21 25 26 27 28 32 31 30 29 33 34 35 36 37 38 39 40 mclr /v pp /re3 ra0 ra1 ra2 ra3 v ddcore /v cap ra5 re0 re1 re2 v dd v ss ra7 ra6 rc0 rc1 rc2 rc3 rd0 rd1 rb3 rb7/pgd rb2 rb1 rb0 v dd v ss rb6/pgc rb5 rb4 rd7 rd6 rd5 rd4 rc7 rc6 rc5 rc4 rd3 rd2 pic18f4xk80 ? pic18lf45k80 ? pic18lf46k80 ? 2011 microchip technology inc. ds39972b-page 5 pic18fxxk80 family figure 2-4: pic18f8xkx x family pin diagrams 44-pin tqfp/qfn the following devices are included in 44-pin tqfp/qfn parts: ? pic18f45k80 ? pic18f46k80 ra1 rb3 ra2 v ddcore /v cap ra5 1 2 3 4 7 5 6 33 32 19 18 15 17 28 27 26 25 24 23 22 8 9 10 11 12 13 14 ra0 mclr /v pp /re3 rb7/pgd rc0 rc1 rc2 rc3 ra3 v ss rb1 rb0 v ss rc4 rc5 rc6 rb6/pgc rb5 rb4 16 20 21 29 30 31 37 38 41 39 34 44 43 42 40 36 35 rc7 rd4 rd5 rd6 rd7 v dd rb2 n/c v dd ra7 ra6 re0 re1 re2 rd0 rd1 rd3 rd2 n/c n/c n/c pic18f4xk80 ? pic18lf45k80 ? pic18lf46k80 pic18fxxk80 family ds39972b-page 6 ? 2011 microchip technology inc. figure 2-5: pic18f8xkx x family pin diagrams 64-pin tqfp/qfn the following devices are included in 64-pin tqfp/qfn parts: ? pic18f65k80 ? pic18f66k80 ra1 rb3 ra2 ra5 1 2 3 4 7 5 6 43 42 24 23 20 22 38 37 36 35 34 33 27 8 9 10 11 17 18 19 ra0 mclr /v pp /re3 rc0 rc1 rc2 rc3 ra3 v ss rb1 rb0 rc4 rc5 rc6 rb6/pgc rb5 rb4 21 25 26 39 40 41 57 58 61 59 54 64 63 62 60 56 55 rc7 rd4 rd5 rd6 rd7 av dd rb2 ra7 ra6 re0 re1 re2 rd0 rd1 rd3 rd2 rf0 12 13 14 15 16 29 28 32 30 31 48 47 44 45 46 52 53 49 51 50 rg0 rg1 v dd rg2 rg3 rg4 rf1 re5 v dd v ss re4 v ddcore /v cap rf2 rf3 a vdd v dd a vss v ss rf4 rf5 rf6 rf7 v ss v dd re6 re7 rb7/pgd pic18f6xk80 ? PIC18LF65K80 ? pic18lf66k80 ? 2011 microchip technology inc. ds39972b-page 7 pic18fxxk80 family 2.3 on-chip voltage regulator the pic18fxxk80 device family is available with or without an internal core voltage regulator. on the devices with a voltage regulator (?pic18 f ? in the part number), the regulator is always enabled. the reg- ulator input is taken from the microcontroller v dd pins. the output of the regulator is supplied internally to the v ddcore /v cap pin. this pin simultaneously serves as both the regulator output and the microcontroller core power input pin. for these devices, a low-esr (< 5 ? ) capacitor is required on the v cap /v ddcore pin to stabi- lize the voltage regulator output voltage. the v cap / v ddcore pin must not be connected to v dd and must use a capacitor that is typically 10 ? f connected to ground. on the devices that do not have a voltage regulator (?pic18 lf ? in the part number), power to the cpu core must be externally supplied through the microcontroller v dd pins. v ddcore /v cap is internally connected to v dd . a 0.1 f capacitor should be connected to the v ddcore / v cap pin. examples are shown in figure 2-6 . the specifications for core voltage and capacitance are listed in section 6.0 ?ac/dc characteristics timing requirements for program/verify test mode? . figure 2-6: conne ctions for the on-chip regulator v dd v ddcore /v cap (2) v ss pic18lfxxk80 3.3v (1) v dd v ddcore /v cap v ss pic18fxxk80 c f 5v (1) regulator enabled (pic18fxxk80 parts): regulator disabled (pic18lfxxk80 parts): note 1: these are typical operating voltages. refer to section 6.0 ?ac/dc characteristics timing requirements for program/verify test mode? . 2: when the regulator is disabled, v ddcore / v cap must be connected to a 0.1 f capacitor. c f pic18fxxk80 family ds39972b-page 8 ? 2011 microchip technology inc. 2.4 memory maps for pic18fx6k80 devices, the code memory space extends from 000000h to 00ffffh (64 kbytes) in four 16-kbyte blocks. for pic18fx5k80 devices, the code memory space extends from 000000h to 007fffh (32 kbytes) in four 8-kbyte blocks. addresses, 0000h through 07ffh or 0fffh, however, define a ?boot block? region that is treated separately from block 0. all of these blocks define code protection boundaries within the code memory space. the size of the boot block in pic18fxxk80 devices can be configured as 1 or 2k words (see table 5-3 ). this is done through the bbsiz bit in the configuration register, config4l (see table 5-1 ). it is important to note that increasing the size of the boot block decreases the size of block 0. table 2-2: implementation of code memory figure 2-7: memory map and the code memory space for pic18fxxk80 devices (1) device code memory size (bytes) pic18f65k80 000000h-007fffh (32k) pic18f45k80 pic18f25k80 PIC18LF65K80 pic18lf45k80 pic18lf25k80 pic18f66k80 000000h-00ffffh (64k) pic18f46k80 pic18f26k80 pic18lf66k80 pic18lf46k80 pic18lf26k80 000000h 200000h 3fffffh 01ffffh note 1: sizes of memory areas are not to scale. 2: boot block size is determined by the bbsiz bit (config4l<4>). code memory unimplemented read as ? 0 ? configuration and id space device/memory size pic18fx6k80 pic18fx5k80 bbsiz = 1 bbsiz = 0 bbsiz = 1 bbsiz = 0 address boot block (2) 2kw boot block (2) boot block (2) 2kw boot block (2) 0000h block 0 7kw block 0 3kw 0800h block 0 6kw block 0 2kw 1000h 1fffh block 1 4kw block 1 4kw 2000h 3fffh block 1 8kw block 1 8kw block 2 4kw block 2 4kw 4000h 5fffh block 3 4kw block 3 4kw 6000h 7fffh block 2 8kw block 2 8kw 8000h bfffh block 3 8kw block 3 8kw c000h ffffh ? 2011 microchip technology inc. ds39972b-page 9 pic18fxxk80 family in addition to the code memory space, there are three blocks in the configuration and id space that are accessible to the user through table reads and table writes. their locations in the memory map are shown in figure 2-8 . users may store identification (id) information in eight id registers. these id registers are mapped in addresses, 200000h through 200007h. the id loca- tions read out normally, even after code protection is applied. locations, 300000h through 30000dh, are reserved for the configuration bits. these bits select various device options and are described in section 5.0 ?configura- tion word? . these configuration bits read out normally, even after code protection. locations, 3ffffeh and 3fffffh, are reserved for the device id bits. these bits may be used by the program- mer to identify what device type is being programmed and are described in section 5.0 ?configuration word? . these device id bits read out normally, even after code protection. 2.4.1 memory address pointer memory in the address space, 0000000h to 3fffffh, is addressed via the table pointer register, which is comprised of three pointer registers: ? tblptru, at ram address 0ff8h ? tblptrh, at ram address 0ff7h ? tblptrl, at ram address 0ff6h the 4-bit command, ? 0000 ? (core instruction), is used to load the table pointer prior to using many read or write operations. tblptru tblptrh tblptrl addr<21:16> addr<15:8> addr<7:0> pic18fxxk80 family ds39972b-page 10 ? 2011 microchip technology inc. figure 2-8: configuration and id locations for pic18fxxk80 family devices id location 1 200000h id location 2 200001h id location 3 200002h id location 4 200003h id location 5 200004h id location 6 200005h id location 7 200006h id location 8 200007h config1l 300000h config1h 300001h config2l 300002h config2h 300003h config3l 300004h config3h 300005h config4l 300006h config4h 300007h config5l 300008h config5h 300009h config6l 30000ah config6h 30000bh config7l 30000ch config7h 30000dh device id1 3ffffeh device id2 3fffffh note: sizes of memory areas are not to scale. 000000h 1fffffh 3fffffh 01ffffh code memory unimplemented read as ? 0 ? configuration and id space 2fffffh ? 2011 microchip technology inc. ds39972b-page 11 pic18fxxk80 family 2.5 high-level overview of the programming process figure 2-9 shows the high-level overview of the programming process. first, a block erase is performed for each block. next, the code memory, id locations and data eeprom are programmed. these memories are then verified to ensure that programming was successful. if no errors are detected, the configuration bits are then programmed and verified. figure 2-9: high-level programming flow 2.6 entering and exiting high-voltage icsp program/verify mode as shown in figure 2-11 , entering high-voltage icsp program/verify mode requires two steps. first, voltage is applied to the mclr pin. second, a 32-bit key sequence is presented on pgd. the programming voltage applied to mclr is v ihh . v ihh must be applied to mclr during the transfer of the key sequence. after v ihh is applied to mclr , an interval of at least p12 must elapse before presenting the key sequence on pgd. the key sequence is a specific 32-bit pattern,? 0100 1101 0100 0011 0100 1000 0101 0000 ? (more easily remembered as 4d434850h in hexadecimal). the device will enter program/verify mode only if the sequence is valid. the most significant bit of the most significant nibble must be shifted in first. once the key sequence is complete, program/verify mode is entered, and the program memory can be accessed and programmed in serial fashion. while in the program/verify mode, all unused i/os are placed in the high-impedance state. exiting program/verify mode is done by removing v ihh from mclr , as shown in figure 2-13 . the only require- ment for exit is that an interval, p16, should elapse between the last clock and the program signals on pgc and pgd before removing v ihh . start program memory program ids program data ee verify program verify ids verify data program configuration bits verify configuration bits done perform sequential block erase procedure pic18fxxk80 family ds39972b-page 12 ? 2011 microchip technology inc. figure 2-10: entering low-voltage program/verify mode figure 2-11: entering high-voltage program/verify mode mclr pgd pgc v dd p1 b31 b30 b29 b28 b27 b2 b1 b0 b3 ... program/verify entry code = 4d434850h p2b p2a p12 01001 0000 v ih v ih p13 mclr pgd pgc v dd p13 p1 b31 b30 b29 b 8 b27 b2 b1 b0 b3 ... program/verify entry code = 4d434850h p2b p2a p12 01001 0000 v ihh ? 2011 microchip technology inc. ds39972b-page 13 pic18fxxk80 family figure 2-12: exiting low-voltage program/verify mode figure 2-13: exiting high-voltage program/verify mode 2.7 entering and exiting low-voltage icsp program/verify mode as shown in figure 2-10 , entering low-voltage icsp program/verify mode requires three steps: 1. the mclr pin is grounded. 2. a 32-bit key sequence is presented on pgd. 3. the mclr pin is brought to v dd the mclr pin must be grounded during the transfer of the key sequence. after mclr is grounded, an interval of at least p12 must elapse before presenting the key sequence on pgd. the key sequence is a specific 32-bit pattern,? 0100 1101 0100 0011 0100 1000 0101 0000 ? (more easily remembered as 4d434850h in hexadecimal). the device will enter program/verify mode only if the sequence is valid. the most significant bit of the most significant nibble must be shifted in first. once the key sequence is complete, v ih , or usually v dd , must be applied to mclr and held at that level for as long as program/verify mode is to be maintained. there is no minimum time requirement before present- ing data on pgd. on successful entry, the program memory can be accessed and programmed in serial fashion. while in the program/verify mode, all unused i/os are placed in the high-impedance state. exiting program/verify mode is done by grounding the mclr again, as shown in figure 2-12 . the only requirement for exit is that an interval, p16, should elapse between the last clock, and the program signals on pgc and pgd before grounding mclr . 2.8 serial program/verify operation the pgc pin is used as a clock input pin, and the pgd pin is used for entering command bits and data input/ output during serial operation. commands and data are transmitted on the rising edge of pgc, latched on the falling edge of pgc, and are least significant bit (lsb) first. 2.8.1 4-bit commands all instructions are 20 bits, consisting of a leading 4-bit command, followed by a 16-bit operand, which depends on the type of command being executed. to input a command, pgc is cycled four times. the com- mands needed for programming and verification are shown in ta b l e 2 - 3 . commands and data are entered lsb first. depending on the 4-bit command, the 16-bit operand represents 16 bits of input data, or 8 bits of input data and 8 bits of output data. throughout this specification, commands and data are presented as illustrated in ta b l e 2 - 4 . the 4-bit command and data are shown most significant bit (msb) first. the command operand, or ?data payload?, is shown as pic18fxxk80 family ds39972b-page 14 ? 2011 microchip technology inc. 2.8.2 core instruction the core instruction passes a 16-bit instruction to the cpu core for execution. this is needed to set up registers, as appropriate, for use with other commands. table 2-3: commands for programming table 2-4: sample command sequence figure 2-14: table write, post-increment timing (? 1101 ?) description 4-bit command core instruction (shift in 16-bit instruction) 0000 shift out tablat register 0010 table read 1000 table read, post-increment 1001 table read, post-decrement 1010 table read, pre-increment 1011 table write 1100 table write, post-increment by 2 1101 table write, start programming, post-increment by 2 1110 table write, start programming 1111 4-bit command data payload core instruction 1101 3c 40 table write, post-increment by 2 1234 pgc p5 pgd pgd = input 5678 1 234 p5a 9 10 11 13 15 16 14 12 fetch next 4-bit command 1011 1234 nnnn p3 p2 p2a 000000 0 10001111 0 04c3 p4 4-bit command 16-bit data payload p2b msb lsb msb lsb lsb msb ? 2011 microchip technology inc. ds39972b-page 15 pic18fxxk80 family 3.0 device programming programming includes the ability to erase or write the various memory regions within the device. in all cases except icsp block erase, the eecon1 register must be configured in order to operate on a particular memory region. when using the eecon1 register to act on code memory, the eepgd bit must be set (eecon1<7> = 1 ) and the cfgs bit must be cleared (eecon1<6> = 0 ). the wren bit must be set (eecon1<2> = 1 ) to enable writes of any sort (e.g., erases) and this must be done prior to initiating a write sequence. the free bit must be set (eecon1<4> = 1 ) in order to erase the program space being pointed to by the table pointer. the erase or write sequence is initiated by setting the wr bit (eecon1<1> = 1 ). it is strongly recommended that the wren bit only be set immediately prior to a program or erase. register 3-1: eecon1 register r/w-x r/w-x u-0 r/w-0 r/w-x r/w-0 r/s-0 r/s-0 eepgd cfgs ? free wrerr (1) wren wr rd bit 7 bit 0 legend: r = readable bit w = writable bit s = bit can be set by software, but not cleared u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 eepgd: flash program or data eeprom memory select bit 1 = access flash program memory 0 = access data eeprom memory bit 6 cfgs: flash program/data eeprom or configuration select bit 1 = access configuration registers 0 = access flash program or data eeprom memory bit 5 unimplemented: read as ? 0 ? bit 4 free: flash row erase enable bit 1 = erase the program memory row addressed by tblptr on the next wr command (cleared by completion of erase operation) 0 = perform write-only bit 3 wrerr: flash program/data eeprom error flag bit (1) 1 = a write operation is prematurely terminated (any reset during self-timed programming in normal operation or an improper write attempt) 0 = the write operation completed bit 2 wren: flash program/data eeprom write enable bit 1 = allows write cycles to flash program/data eeprom 0 = inhibits write cycles to flash program/data eeprom bit 1 wr: write control bit 1 = initiates a data eeprom erase/write cycle or a program memory erase/write cycle (the operation is self-timed and the bit is cleared by hardware once the write is complete. the wr bit can only be set (not cleared) in software.) 0 = write cycle to the eeprom is complete bit 0 rd: read control bit 1 = initiates an eeprom read (read takes one cycle. rd is cleared in hardware. the rd bit can only be set (not cleared) in software. the rd bit cannot be set when eepgd = 1 or cfgs = 1 .) 0 = does not initiate an eeprom read note 1: when a wrerr occurs, the eepgd and cfgs bits are not cleared. this allows tracing of the error condition. pic18fxxk80 family ds39972b-page 16 ? 2011 microchip technology inc. 3.1 icsp erase 3.1.1 icsp block erase erasing code or data eeprom is accomplished by config- uring three block erase control registers, located at 3c0004h through 3c0006h. code memory can only be erased, portions at a time. in order to erase the entire device, every block must be erased sequentially. block erase operations will also clear any code-protect settings associated with the memory block being erased. erase options are detailed in table 3-1 . data eeprom is erased at the same time as all block erase commands. in order to erase data eeprom by itself, the first code sequence in table 3-1 must be used. if the entire device is being erased, this code is not necessary. table 3-1: block erase operations the actual block erase function is a self-timed operation. once the erase has started (falling edge of the 4th pgc after the nop command), serial execution will cease until the erase completes (parameter p11). during this time, pgc may continue to toggle, but pgd must be held low. the code sequence to erase the entire device is shown in tab l e 3 - 2 through table 3-7 and the flowchart is shown in figure 3-1 . the code sequence to just erase data eeprom is shown in table 3-8 . table 3-2: erase block 0 table 3-3: erase block 1 table 3-4: erase block 2 description data (3c0006h:3c0004h) erase data eeprom 800004h erase boot block 800005h erase config bits 800002h erase code eeprom block 0 800104h erase code eeprom block 1 800204h erase code eeprom block 2 800404h erase code eeprom block 3 800804h note: a block erase is the only way to repro- gram code-protect bits from an on state to an off state. 4-bit command data payload core instruction 0000 0000 0000 0000 0000 0000 1100 0000 0000 1100 0000 0000 1100 0000 0000 0e 3c 6e f8 0e 00 6e f7 0e 04 6e f6 04 04 0e 05 6e f6 01 01 0e 06 6e f6 80 80 00 00 00 00 movlw 3ch movwf tblptru movlw 00h movwf tblptrh movlw 04h movwf tblptrl write 04h to 3c0004h movlw 05h movwf tblptrl write 01h to 3c0005h movlw 06h movwf tblptrl write 80h to 3c0006h to erase block 0 nop hold pgd low until erase completes 4-bit command data payload core instruction 0000 0000 0000 0000 0000 0000 1100 0000 0000 1100 0000 0000 1100 0000 0000 0e 3c 6e f8 0e 00 6e f7 0e 04 6e f6 04 04 0e 05 6e f6 02 02 0e 06 6e f6 80 80 00 00 00 00 movlw 3ch movwf tblptru movlw 00h movwf tblptrh movlw 04h movwf tblptrl write 04h to 3c0004h movlw 05h movwf tblptrl write 02h to 3c0005h movlw 06h movwf tblptrl write 80h to 3c0006h to erase block 1 nop hold pgd low until erase completes 4-bit command data payload core instruction 0000 0000 0000 0000 0000 0000 1100 0000 0000 1100 0000 0000 1100 0000 0000 0e 3c 6e f8 0e 00 6e f7 0e 04 6e f6 04 04 0e 05 6e f6 04 04 0e 06 6e f6 80 80 00 00 00 00 movlw 3ch movwf tblptru movlw 00h movwf tblptrh movlw 04h movwf tblptrl write 04h to 3c0004h movlw 05h movwf tblptrl write 04h to 3c0005h movlw 06h movwf tblptrl write 80h to 3c0006h to erase block 2 nop hold pgd low until erase completes ? 2011 microchip technology inc. ds39972b-page 17 pic18fxxk80 family table 3-5: erase block 3 table 3-6: erase boot block table 3-7: eras e configuration fuses table 3-8: erase data eeprom 4-bit command data payload core instruction 0000 0000 0000 0000 0000 0000 1100 0000 0000 1100 0000 0000 1100 0000 0000 0e 3c 6e f8 0e 00 6e f7 0e 04 6e f6 04 04 0e 05 6e f6 08 08 0e 06 6e f6 80 80 00 00 00 00 movlw 3ch movwf tblptru movlw 00h movwf tblptrh movlw 04h movwf tblptrl write 04h to 3c0004h movlw 05h movwf tblptrl write 08h to 3c0005h movlw 06h movwf tblptrl write 80h to 3c0006h to erase block 3 nop hold pgd low until erase completes 4-bit command data payload core instruction 0000 0000 0000 0000 0000 0000 1100 0000 0000 1100 0000 0000 1100 0000 0000 0e 3c 6e f8 0e 00 6e f7 0e 04 6e f6 05 05 0e 05 6e f6 00 00 0e 06 6e f6 80 80 00 00 00 00 movlw 3ch movwf tblptru movlw 00h movwf tblptrh movlw 04h movwf tblptrl write 05h to 3c0004h movlw 05h movwf tblptrl write 00h to 3c0005h movlw 06h movwf tblptrl write 80h to 3c0006h to erase boot block nop hold pgd low until erase completes 4-bit command data payload core instruction 0000 0000 0000 0000 0000 0000 1100 0000 0000 1100 0000 0000 1100 0000 0000 0e 3c 6e f8 0e 00 6e f7 0e 04 6e f6 02 02 0e 05 6e f6 00 00 0e 06 6e f6 80 80 00 00 00 00 movlw 3ch movwf tblptru movlw 00h movwf tblptrh movlw 04h movwf tblptrl write 02h to 3c0004h movlw 05h movwf tblptrl write 00h to 3c0005h movlw 06h movwf tblptrl write 80h to 3c0006h to erase configuration fuses nop hold pgd low until erase completes 4-bit command data payload core instruction 0000 0000 0000 0000 0000 0000 1100 0000 0000 1100 0000 0000 1100 0000 0000 0e 3c 6e f8 0e 00 6e f7 0e 04 6e f6 04 04 0e 05 6e f6 00 00 0e 06 6e f6 80 80 00 00 00 00 movlw 3ch movwf tblptru movlw 00h movwf tblptrh movlw 04h movwf tblptrl write 04h to 3c0004h movlw 05h movwf tblptrl write 00h to 3c0005h movlw 06h movwf tblptrl write 80h to 3c0006h to erase data eeprom nop hold pgd low until erase completes pic18fxxk80 family ds39972b-page 18 ? 2011 microchip technology inc. figure 3-1: block erase flow start write 80h to 3c0006h to erase block 0 write 04h delay p11 + p10 time to 3c0004h write 01h to 3c0005h write 80h to 3c0006h to erase block 1 write 04h delay p11 + p10 time to 3c0004h write 02h to 3c0005h write 80h to 3c0006h to erase block 2 write 04h delay p11 + p10 time to 3c0004h write 04h to 3c0005h write 80h to 3c0006h to erase block 3 write 04h delay p11 + p10 time to 3c0004h write 08h to 3c0005h write 80h to 3c0006h to erase boot block write 05h delay p11 + p10 time to 3c0004h write 00h to 3c0005h write 80h to 3c0006h to erase config. fuses write 02h delay p11 + p10 time to 3c0004h write 00h to 3c0005h done ? 2011 microchip technology inc. ds39972b-page 19 pic18fxxk80 family figure 3-2: blo ck erase timing 3.1.2 icsp row erase it is possible to erase one row (64 bytes of data) provided the block is not code or write-protected. rows are located at static boundaries beginning at program memory address, 000000h, extending to the internal program memory limit (see section 2.4 ?memory maps? ). the row erase duration is externally timed and is controlled by pgc. after the wr bit in eecon1 is set, a nop is issued, where the 4th pgc is held high for the duration of the programming time, p9. after pgc is brought low, the programming sequence is terminated. pgc must be held low for the time specified by parameter p10 to allow high-voltage discharge of the memory array. the code sequence to ro w erase a pic18fxxk80 family device is shown in table 3-9 . the flowchart shown in figure 3-3 depicts the logic necessary to completely erase a pic18fxxk80 family device. the timing diagram that details the start programming command and parameters p9 and p10 is shown in figure 3-4 . n 1234 1 21516 123 pgc p5 p5a pgd pgd = input 0 0011 p11 p10 erase time 000000 12 00 4 0 1 2 15 16 p5 123 p5a 4 0000 n 4-bit command 4-bit command 4-bit command 16-bit data payload 16-bit data payload 16-bit data payload 11 note: the tblptr register can point to any byte within the row intended for erase. pic18fxxk80 family ds39972b-page 20 ? 2011 microchip technology inc. table 3-9: single row erase code memory code sequence figure 3-3: single row er ase code memory flow 4-bit command data payload core instruction step 1: direct access to code memory and enable writes. 0000 0000 0000 8e 7f 9c 7f 84 7f bsf eecon1, eepgd bcf eecon1, cfgs bsf eecon1, wren step 2: point to first row in code memory. 0000 0000 0000 6a f8 6a f7 6a f6 clrf tblptru clrf tblptrh clrf tblptrl step 3: enable erase and erase single row. 0000 0000 0000 88 7f 82 7f 00 00 bsf eecon1, free bsf eecon1, wr nop ? hold pgc high for time p9 and low for time p10. step 4: repeat step 3 with address pointer incremented by 64 until all rows are erased. done start hold pgc low for time p10 all rows done? no yes addr = 0 configure device for row erases addr = addr + 64 start erase sequence and hold pgc high for time p9 ? 2011 microchip technology inc. ds39972b-page 21 pic18fxxk80 family 3.2 code memory programming programming code memory is accomplished by first loading data into the write buffer and then initiating a programming sequence. the write and erase buffer sizes, shown in table 3-10, can be mapped to any location of the same size beginning at 000000h. the actual memory write sequence takes the contents of this buffer and programs the proper amount of code memory that contains the table pointer. the programming duration is externally timed and is controlled by pgc. after a start programming command is issued (4-bit command, ? 1111 ?), a nop is issued, where the 4th pgc is held high for the duration of the programming time, p9. after pgc is brought low, the programming sequence is terminated. pgc must be held low for the time specified by parameter p10 to allow high-voltage discharge of the memory array. the code sequence to program a pic18fxxk80 family device is shown in table 3-11 . the flowchart, shown in figure 3-6 , depicts the logic necessary to completely write a pic18fxxk80 family device. the timing diagram that details the start programming command, and parameters p9 and p10 is shown in figure 3-4 . table 3-10: write and erase buffer sizes figure 3-4: table write and start programming instruction timing (? 1111 ?) note: the tblptr register must point to the same region when initiating the program- ming sequence as it did when the write buffers were loaded. all devices write buffer size in bytes erase buffer size in bytes pic18fxxk80 64 64 1234 12 1516 123 4 pgc p5a pgd pgd = input n 11 1 1 34 6 5 p9 (1) p10 programming time nnn nn n n 00 12 0 00 16-bit data payload 0 3 0 p5 4-bit command 16-bit data payload 4-bit command note 1: use p9a for user id and configuration word programming. pic18fxxk80 family ds39972b-page 22 ? 2011 microchip technology inc. figure 3-5: erase and write boundaries panel 2 panel 1 tblptr<5:0> = 63 . . . . . tblptr<5:0> = 0 64-byte write buffer tblptr<5:0> = 63 . . . . . tblptr<5:0> = 0 64-byte write buffer offset = tblptr<15:6> offset = tblptr<15:6> tblptr<21:16> = 1 tblptr<21:16> = 0 erase region 64 bytes erase region 64 bytes note: tblptr = tblptru:tblptrh:tblptrl. ? 2011 microchip technology inc. ds39972b-page 23 pic18fxxk80 family 3.2.1 programming a maximum of 64 bytes can be programmed into the block referenced by tblptr<21:6>. the panel that will be written will automatically be enabled based on the value of the table pointer. table 3-11: write code memory code sequence for programming 4-bit command data payload core instruction step 1: direct access to code memory and enable writes. 0000 0000 0000 8e 7f 9c 7f 84 7f bsf eecon1, eepgd bcf eecon1, cfgs bsf eecon1, wren step 2: point to row to be written. 0000 0000 0000 0000 0000 0000 0e pic18fxxk80 family ds39972b-page 24 ? 2011 microchip technology inc. figure 3-6: program code memory flow start write sequence all locations done? no done start yes load 2 bytes to write buffer at ? 2011 microchip technology inc. ds39972b-page 25 pic18fxxk80 family 3.2.2 modifying code memory the previous programming example assumed that the device had been erased entirely prior to programming (see section 3.1.1 ?icsp block erase? ). it may be the case, however, that the user wishes to modify only a section of an already programmed device. the appropriate number of by tes required for the erase buffer must be read out of code memory (as described in section 4.2 ?verify code memory and id loca- tions? ) and buffered. modifications can be made on this buffer. then, the block of code memory that was read out must be erased and rewritten with the modified data (see section 3.2.1 ?programming? ). the wren bit must be set if the wr bit in eecon1 is used to initiate a write sequence. table 3-12: modifying code memory 4-bit command data payload core instruction step 1: direct access to code memory. step 2: read and modify code memory (see section 4.1 ?read code memory, id locations and configuration bits? ). 0000 0000 8e 7f 9c 7f bsf eecon1, eepgd bcf eecon1, cfgs step 3: set the table pointer for the block to be erased. 0000 0000 0000 0000 0000 0000 0e pic18fxxk80 family ds39972b-page 26 ? 2011 microchip technology inc. 3.3 data eeprom programming data eeprom is accessed, one byte at a time, via an address pointer (register pair, eeadrh:eeadr) and a data latch (eedata). data eeprom is written by loading eeadrh:eeadr with the desired memory location, eedata with the data to be written and initiating a memory write by appropriately configuring the eecon1 register ( register 3-1 ). a byte write auto- matically erases the location and writes the new data (erase-before-write). when using the eecon1 register to perform a data eeprom write, both the eepgd and cfgs bits must be cleared (eecon1<7:6> = 00 ). the wren bit must be set (eecon1<2> = 1 ) to enable writes of any sort and this must be done prior to initiating a write sequence. the write sequence is initiated by setting the wr bit (eecon1<1> = 1 ). the write begins on the falling edge of the 4th pgc after the wr bit is set. it ends when the wr bit is cleared by hardware. after the programming sequence terminates, pgc must still be held low for the time specified by parameter p10 to allow high-voltage discharge of the memory array. figure 3-7: program data flow figure 3-8: data eeprom write timing start start write set data done no yes done? enable write sequence set address wr bit clear? no yes n pgc pgd pgd = input 0000 bsf eecon1, wr 4-bit command 1234 1 21516 p5 p5a p10 12 n poll wr bit, repeat until clear 16-bit data payload 1234 1 21516 123 p5 p5a 4 12 1516 p5 p5a 0000 movf eecon1, w, 0 4-bit command 0000 4-bit command shift out data movwf tablat pgc pgd (see below) (see figure 4-4) pgd = input pgd = output poll wr bit p11a ? 2011 microchip technology inc. ds39972b-page 27 pic18fxxk80 family table 3-13: programming data memory 4-bit command data payload core instruction step 1: direct access to data eeprom. 0000 0000 9e 7f 9c 7f bcf eecon1, eepgd bcf eecon1, cfgs step 2: set the data eeprom address pointer. 0000 0000 0000 0000 0e pic18fxxk80 family ds39972b-page 28 ? 2011 microchip technology inc. 3.4 id location programming the id locations are programmed much like the code memory. the id registers are mapped in addresses, 200000h through 200007h. these locations read out normally even after code protection. table 3-14 demonstrates the code sequence required to write the id locations. in order to modify the id locations, refer to the method- ology described in section 3.2.2 ?modifying code memory? . as with code memory, the id locations must be erased before being modified. table 3-14: write id sequence note: the user only needs to fill the first 8 bytes of the write buffer in order to write the id locations. 4-bit command data payload core instruction step 1: direct access to code memory and enable writes. 0000 0000 8e 7f 9c 7f bsf eecon1, eepgd bcf eecon1, cfgs step 2: load write buffer with 8 bytes and write. 0000 0000 0000 0000 0000 0000 1101 1101 1101 1111 0000 0e 20 6e f8 0e 00 6e f7 0e 00 6e f6 ? 2011 microchip technology inc. ds39972b-page 29 pic18fxxk80 family 3.5 boot block programming the code sequence detailed in table 3-11 should be used, except that the address used in ?step 2? will be in the range of 000000h to 0007ffh, or 000000h to 000fffh, as defined by the bbsiz bit in the config4l register (see tab l e 5 - 1 ). 3.6 configuration bits programming unlike code memory, the configuration bits are programmed a byte at a time. the table write, begin programming 4-bit command (? 1111 ?) is used, but only 8 bits of the following 16-bit payload will be written. the lsb of the payload will be written to even addresses and the msb will be written to odd addresses. the code sequence to program two consecutive configuration locations is shown in ta bl e 3 - 1 5 . table 3-15: set address pointe r to configuration location figure 3-9: configurat ion programming flow note: the address must be explicitly written for each byte programmed. the addresses can not be incremented in this mode. 4-bit command data payload core instruction step 1: enable writes and direct access to configuration memory. 0000 0000 8e 7f 8c 7f bsf eecon1, eepgd bsf eecon1, cfgs step 2: set table pointer for configuration byte to be written; write even/odd addresses. (1) 0000 0000 0000 0000 0000 0000 1111 0000 0000 0000 1111 0000 0e 30 6e f8 0e 00 6e f7 0e 00 6e f6 pic18fxxk80 family ds39972b-page 30 ? 2011 microchip technology inc. 4.0 reading the device 4.1 read code memory, id locations and configuration bits code memory is accessed, one byte at a time, via the 4-bit command, ? 1001 ? (table read, post-increment). the contents of memory pointed to by the table pointer (tblptru:tblptrh:tblptrl) are serially output on pgd. the 4-bit command is shifted in, lsb first. the read is executed during the next 8 clocks, then shifted out on pgd during the last 8 clocks, lsb to msb. a delay of p6 must be introduced after the falling edge of the 8th pgc of the operand to allow pgd to transition from an input to an output. during this time, pgc must be held low (see figure 4-1 ). this operation also increments the table pointer by one, pointing to the next byte in code memory for the next read. this technique will work to read any memory in the 000000h to 3fffffh address space, so it also applies to reading the id and configuration registers. table 4-1: read code memory sequence figure 4-1: table read, post-in crement instruction timing (? 1001 ?) 4-bit command data payload core instruction step 1: set table pointer. 0000 0000 0000 0000 0000 0000 0e ? 2011 microchip technology inc. ds39972b-page 31 pic18fxxk80 family 4.2 verify code memory and id locations the verify step involves reading back the code memory space and comparing it against the copy held in the programmer?s buffer. memory reads occur a single byte at a time, so two bytes must be read to compare against the word in the programmer?s buffer. refer to section 4.1 ?read code memory, id locations and configuration bits? for implementation details of reading code memory. the table pointer must be manually set to 200000h (base address of the id locations) once the code memory has been verified. the post-increment feature of the table read, 4-bit command may not be used to increment the table pointer beyond the code memory space. in a 128-kbyte device, for example, a post-increment read of address, 1ffffh, will wrap the table pointer back to 000000h, rather than point to the unimplemented address, 020000h. figure 4-2: verify code memory flow read low byte read high byte does word = expect data? failure, report error all code memory verified? no yes no set tblptr = 0 start set tblptr = 200000h yes read low byte read high byte does word = expect data? failure, report error all id locations verified? no yes done yes no with post-increment with post-increment increment pointer with post-increment with post-increment pic18fxxk80 family ds39972b-page 32 ? 2011 microchip technology inc. 4.3 verify configuration bits a configuration address may be read and output on pgd via the 4-bit command, ? 1001 ?. configuration data is read and written in a byte-wise fashion, so it is not necessary to merge two bytes into a word prior to a compare. the result may then be immediately compared to the appropriate configuration data in the programmer?s memory for verification. refer to section 4.1 ?read code memory, id locations and configuration bits? for implementation details of reading configuration data. 4.4 read data eeprom memory data eeprom is accessed, one byte at a time, via an address pointer (register pair, eeadrh:eeadr) and a data latch (eedata). data eeprom is read by loading eeadrh:eeadr with the desired memory location and initiating a memory read by appropriately configuring the eecon1 register ( register 3-1 ). the data will be loaded into eedata, where it may be serially output on pgd via the 4-bit command, ? 0010 ? (shift out data holding register). a delay of p6 must be introduced after the falling edge of the 8th pgc of the operand to allow pgd to transition from an input to an output. during this time, pgc must be held low (see figure 4-4 ). the command sequence to read a single byte of data is shown in table 4-2 . figure 4-3: read data eeprom flow table 4-2: read data eeprom memory start set address read byte done no yes done? move to tablat shift out data 4-bit command data payload core instruction step 1: direct access to data eeprom. 0000 0000 9e 7f 9c 7f bcf eecon1, eepgd bcf eecon1, cfgs step 2: set the data eeprom address pointer. 0000 0000 0000 0000 0e ? 2011 microchip technology inc. ds39972b-page 33 pic18fxxk80 family figure 4-4: shift out data holding register timing (? 0010 ?) 4.5 verify data eeprom a data eeprom address may be read via a sequence of core instructions (4-bit command, ? 0000 ?) and then output on pgd via the 4-bit command, ? 0010 ? (tablat register). the result may then be immediately com- pared to the appropriate data in the programmer?s memory for verification. refer to section 4.4 ?read data eeprom memory? for implementation details of reading data eeprom. 4.6 blank check the term, ?blank check?, means to verify that the device has no programmed memory cells. all memories must be verified: code memory, data eeprom, id locations and configuration bits. the device id registers (3ffffeh:3fffffh) should be ignored. a ?blank? or ?erased? memory cell will read as a ? 1 ?. so, blank checking a device merely means to verify that all bytes read as ffh, except the configuration bits. unused (reserved) configuration bits will read ? 0 ? (pro- grammed). refer to table 5-1 for blank configuration expect data for the various pic18fxxk80 family devices. given that blank checking is merely code and data eeprom verification with ffh expect data, refer to section 4.4 ?read data eeprom memory? and section 4.2 ?verify code memory and id locations? for implementation details. figure 4-5: blank check flow 1234 pgc p5 pgd pgd = input shift data out p6 pgd = output 5678 1234 p5a 91011 13 1516 14 12 fetch next 4-bit command 0100 pgd = input lsb msb 12 34 56 12 34 nnnn p14 yes no start blank check device is device blank? continue abort pic18fxxk80 family ds39972b-page 34 ? 2011 microchip technology inc. 5.0 configuration word the pic18fxxk80 family of devices has several configuration words. these bits can be set or cleared to select various device configurations. all other memory areas should be programmed and verified prior to setting the configuration words. these bits may be read out normally, even after read or code protection. see table 5-1 for a list of configuration bits and device ids, and table 5-3 for the configuration bit descriptions. 5.1 id locations a user may store identification (id) information in eight id locations, mapped in 200000h:200007h. it is recom- mended that the most significant nibble of each id be fh. in doing so, if the user code inadvertently tries to execute from the id space, the id data will execute as a nop . table 5-1: configuratio n bits and device ids file name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default/ unprogrammed value 300000h config1l ?xinst ? soscsel1 soscsel0 intoscsel ?reten -1-1 11-1 300001h config1h ieso fcmen ? pllcfg fosc3 fosc2 fosc1 fosc0 00-0 1000 300002h config2l ? borpw1 borpw0 borv1 borv0 boren1 boren0 pwrten -111 1111 300003h config2h ? wdtps4 wdtps3 wdtps2 wdtps1 wdtps0 wdten1 wdten0 -111 1111 300005h config3h mclre ? ? ? msspmsk t3ckmx (1,3) t0ckmx (1) canmx 1--- 1111 300006h config4l debug ? ?bbsiz ? ? ?stvren 1--1 ---1 300008h config5l ? ? ? ? cp3 cp2 cp1 cp0 ---- 1111 300009h config5h cpd cpb ? ? ? ? ? ? 11-- ---- 30000ah config6l ? ? ? ? wrt3 wrt2 wrt1 wrt0 ---- 1111 30000bh config6h wrtd wrtb wrtc ? ? ? ? ? 111- ---- 30000ch config7l ? ? ? ? ebtr3 ebtr2 ebtr1 ebtr0 ---- 1111 30000dh config7h ?ebtrb ? ? ? ? ? ? -1-- ---- 3ffffeh devid1 (2) dev2 dev1 dev0 rev4 rev3 rev2 rev1 rev0 xxxx xxxx 3fffffh devid2 (2) dev10 dev9 dev8 dev7 dev6 dev5 dev4 dev3 xxxx xxxx legend: x = unknown, u = unchanged, ? = unimplemented, q = value depends on condition. shaded cells are unimplemented, read as ? 0 ?. note 1: only implemented in 64-pin devices. 2: see register 28-13 in the ?pic18f66k80 family data sheet? for devid1 values. devid registers are read-only and cannot be programmed by the user. 3: this bit must be maintained as ? 0 ? on 28-pin pic18f2xk80 and 40/44-pin pic18f4xk80 devices. ? 2011 microchip technology inc. ds39972b-page 35 pic18fxxk80 family 5.2 device id word the device id word (devid<2:1>) for the pic18fxxk80 family of devices is located at 3ffffeh:3fffffh. these bits may be used by the programmer to identify what device type is being programmed and read out normally, even after code or read protection. see ta b l e 5 - 2 for a complete list of device id values. figure 5-1: read device id word flow table 5-2: device id value start set tblptr = 3ffffe done read low byte read high byte with post-increment with post-increment device device id value devid2 devid1 pic18f66k80 60h 111x xxxx pic18f46k80 61h 000x xxxx pic18f26k80 61h 001x xxxx pic18f65k80 61h 010x xxxx pic18f45k80 61h 011x xxxx pic18f25k80 61h 100x xxxx pic18lf66k80 61h 110x xxxx pic18lf46k80 61h 111x xxxx pic18lf26k80 62h 000x xxxx PIC18LF65K80 62h 001x xxxx pic18lf45k80 62h 010x xxxx pic18lf25k80 62h 011x xxxx note: the ? x ?s in devid1 contain the device revision code. pic18fxxk80 family ds39972b-page 36 ? 2011 microchip technology inc. table 5-3: pic18fxxk80 family configuration bi t descriptions bit name configuration words description xinst config1l extended instruction set enable bit 1 = instruction set extension and indexed addressing mode enabled 0 = instruction set extension and indexed addressing mode disabled (legacy mode) soscsel<1:0> config1l sosc power selection and mode configuration bits 11 = high-power sosc circuit selected 10 = digital (sclki) mode 01 = low-power sosc circuit selected 00 = reserved intoscsel config1l lf-intosc low-power enable bit 1 = lf-intosc in high-power mode during sleep 0 = lf-intosc in low-power mode during sleep reten config1l vreg sleep enable bit 1 = ultra low-power regulator is disabled. r egulator power in sleep mode is controlled by vregslp (wdtcon<7>). 0 = ultra low-power regulator is enabled. r egulator power in sleep mode is controlled by sreten (wdtcon<4>). ieso config1h internal external switchover bit 1 = two-speed start-up is enabled 0 = two-speed start-up is disabled fcmen config1h fail-safe clock monitor enable bit 1 = fail-safe clock monitor is enabled 0 = fail-safe clock monitor is disabled pllcfg config1h 4 x pll enable bit 1 = oscillator is multiplied by 4 0 = oscillator is used directly fosc<3:0> config1h oscillator selection bits 1101 = ec1, ec oscillator (low power, dc-160 khz) 1100 = ec1io, ec oscillator with clkout function on ra6 (low power, dc-160 khz) 1011 = ec2, ec oscillator (medium power, 160 khz-16 mhz) 1010 = ec2io, ec oscillator with clkout function on ra6 (medium power, 160 khz-16 mhz) 1001 = intio1 internal rc oscillator with clkout function on ra6 1000 = intio2 internal rc oscillator 0111 = rc external rc oscillator 0110 = rcio external rc oscillator with cklout function on ra6 0101 = ec3, ec oscillator (high power, 16 mhz-64 mhz) 0100 = ec3io, ec oscillator with clkout function on ra6 (high power, 16 mhz-64 mhz) 0011 = hs1, hs oscillator (medium power, 4 mhz-16 mhz) 0010 = hs2, hs oscillator (high power, 16 mhz-25 mhz) 0001 = xt oscillator 0000 = lp oscillator borpwr<1:0> config2l bormv power level bits 11 = zpbormv instead of bormv is selected 10 = bormv is set to high-power level 01 = bormv is set to medium power level 00 = bormv is set to low-power level borv<1:0> config2l brown-out reset voltage bits 11 = v bor set to 1.8v 10 = v bor set to 2.0v 01 = v bor set to 2.7v 00 = v bor set to 3.0v note 1: the bbsiz bit cannot be changed once any of the following code-protect bits are enabled: cpb or cp0, wrtb or wrt0, ebtrb or ebtr0. 2: available on pic18f6xkxx devices only. 3: this bit must be maintained as ? 0 ? on 28-pin pic18f2xk80 and 40 -pin pic18f4xk80 devices. ? 2011 microchip technology inc. ds39972b-page 37 pic18fxxk80 family boren<1:0> config2l brown-out reset enable bits 11 = brown-out reset is enabled in hardware only (sboren is disabled) 10 = brown-out reset is enabled in hardware only and disabled in sleep mode (sboren is disabled) 01 = brown-out reset is enabled and controlled by software (sboren is enabled) 00 = brown-out reset is disabled in hardware and software pwrten config2l power-up timer enable bit 1 = pwrt is disabled 0 = pwrt is enabled wdtps<4:0> config2h watchdog timer postscale select bits 10101 - 11111 : reserved 10100 = 1:1048576 10011 = 1:524288 10010 = 1:262144 10001 = 1:131072 10000 = 1:65536 01111 = 1:32,768 01110 = 1:16,384 01101 = 1:8,192 01100 = 1:4,096 01011 = 1:2,048 01010 = 1:1,024 01001 = 1:512 01000 = 1:256 00111 = 1:128 00110 = 1:64 00101 = 1:32 00100 = 1:16 00011 = 1:8 00010 = 1:4 00001 = 1:2 00000 = 1:1 wdten<1:0> config2h watchdog timer enable bits 11 = wdt is enabled in hardware; swdten bit is disabled 10 = wdt is controlled with the swdten bit setting 01 = wdt is enabled only while device is active and disabled in sleep; swdten bit is disabled 00 = wdt is disabled in hardware; swdten bit is disabled mclre config3h mclr pin enable bit 1 = mclr pin is enabled, re3 input pin is disabled 0 = re3 input pin is enabled, mclr pin is disabled msspmsk config3h mssp v3 7-bit address masking mode enable bit 1 = 7-bit address masking mode enable 0 = 5-bit address masking mode enable t3ckmx (2,3) config3h timer3 clock input mux bit 1 = timer3 gets its clock input from the t1cki input when t3con(soscen) = 0 0 = timer3 gets its clock input from the t3cki input when t3con(soscen) = 0 t0ckmx (2) config3h timer0 clock input mux bit 1 = timer0 gets its clock input from the rb5/t0cki pin 0 = timer0 gets its clock input from the rg4/t0cki pin canmx config3h ecan mux bit 1 = ecan tx and rx pins are located on rb2 and rb3, respectively 0 = ecan tx and rx pins are located on rc6 and rc7, respectively (28-pin and 44-pin packages) or on re5 and re4, respectively (64-pin package) table 5-3: pic18fxxk80 family config uration bit descriptions (continued) bit name configuration words description note 1: the bbsiz bit cannot be changed once any of the following code-protect bits are enabled: cpb or cp0, wrtb or wrt0, ebtrb or ebtr0. 2: available on pic18f6xkxx devices only. 3: this bit must be maintained as ? 0 ? on 28-pin pic18f2xk80 and 40-pin pic18f4xk80 devices. pic18fxxk80 family ds39972b-page 38 ? 2011 microchip technology inc. debug config4l background debugger enable bit 1 = background debugger is disabled, rb6 and rb7 are configured as general purpose i/o pins 0 = background debugger is enabled, rb6 and rb7 are dedicated to in-circuit debug bbsiz (1) config4l boot block size select bit 1 = 2k word boot block size 0 = 1k word boot block size stvren config4l stack overflow/underflow reset enable bit 1 = reset on stack overflow/underflow is enabled 0 = reset on stack overflow/underflow is disabled cp3 config5l code protection bit (block 3 code memory area) 1 = block 3 is not code-protected 0 = block 3 is code-protected cp2 config5l code protection bit (block 2 code memory area) 1 = block 2 is not code-protected 0 = block 2 is code-protected cp1 config5l code protection bit (block 1 code memory area) 1 = block 1 is not code-protected 0 = block 1 is code-protected cp0 config5l code protection bit (block 0 code memory area) 1 = block 0 is not code-protected 0 = block 0 is code-protected cpd config5h code protection bit (data eeprom) 1 = data eeprom is not code-protected 0 = data eeprom is code-protected cpb config5h code protection bit (boot block memory area) 1 = boot block is not code-protected 0 = boot block is code-protected wrt3 config6l write protection bit (block 3 code memory area) 1 = block 3 is not write-protected 0 = block 3 is write-protected wrt2 config6l write protection bit (block 2 code memory area) 1 = block 2 is not write-protected 0 = block 2 is write-protected wrt1 config6l write protection bit (block 1 code memory area) 1 = block 1 is not write-protected 0 = block 1 is write-protected wrt0 config6l write protection bit (block 0 code memory area) 1 = block 0 is not write-protected 0 = block 0 is write-protected wrtd config6h write protection bit (data eeprom) 1 = data eeprom is not write-protected 0 = data eeprom is write-protected wrtb config6h write protection bit (boot block memory area) 1 = boot block is not write-protected 0 = boot block is write-protected wrtc config6h write protection bit (configuration registers) 1 = configuration registers are not write-protected 0 = configuration registers are write-protected ebtr3 config7l table read protection bit (block 3 code memory area) 1 = block 3 is not protected from table reads executed in other blocks 0 = block 3 is protected from t able reads executed in other blocks table 5-3: pic18fxxk80 family config uration bit descriptions (continued) bit name configuration words description note 1: the bbsiz bit cannot be changed once any of the following code-protect bits are enabled: cpb or cp0, wrtb or wrt0, ebtrb or ebtr0. 2: available on pic18f6xkxx devices only. 3: this bit must be maintained as ? 0 ? on 28-pin pic18f2xk80 and 40 -pin pic18f4xk80 devices. ? 2011 microchip technology inc. ds39972b-page 39 pic18fxxk80 family ebtr2 config7l table read protection bit (block 2 code memory area) 1 = block 2 is not protected from table reads executed in other blocks 0 = block 2 is protected from t able reads executed in other blocks ebtr1 config7l table read protection bit (block 1 code memory area) 1 = block 1 is not protected from table reads executed in other blocks 0 = block 1 is protected from t able reads executed in other blocks ebtr0 config7l table read protection bit (block 0 code memory area) 1 = block 0 is not protected from table reads executed in other blocks 0 = block 0 is protected from t able reads executed in other blocks ebtrb config7h table read protection bit (boot block memory area) 1 = boot block is not protected from table reads executed in other blocks 0 = boot block is protected from table reads executed in other blocks dev<10:3> devid2 device id bits these bits are used with the dev<2:0> bits in the devid1 register to identify the part number. dev<2:0> devid1 device id bits these bits are used with the dev<10:3> bits in the devid2 register to identify the part number. rev<4:0> devid1 revision id bits these bits are used to indicate the revision of the device. table 5-3: pic18fxxk80 family config uration bit descriptions (continued) bit name configuration words description note 1: the bbsiz bit cannot be changed once any of the following code-protect bits are enabled: cpb or cp0, wrtb or wrt0, ebtrb or ebtr0. 2: available on pic18f6xkxx devices only. 3: this bit must be maintained as ? 0 ? on 28-pin pic18f2xk80 and 40-pin pic18f4xk80 devices. pic18fxxk80 family ds39972b-page 40 ? 2011 microchip technology inc. 5.3 embedding configuration word information in the hex file to allow portability of code, a pic18fxxk80 device programmer is required to read the configuration word locations from the hex file. if configuration word information is not present in the hex file, then a simple warning message should be issued. similarly, while saving a hex file, all configuration word information must be included. an option to not include the configu- ration word information may be provided. when embedding configuration word information in the hex file, it should start at address, 300000h. microchip technology inc. feels strongly that this feature is important for the benefit of the end customer. 5.4 embedding data eeprom information in the hex file to allow portability of code, a pic18fxxk80 device programmer is required to read the data eeprom information from the hex file. if data eeprom informa- tion is not present, a simple warning message should be issued. similarly, when saving a hex file, all data eeprom information must be included. an option to not include the data eeprom information may be provided. when embedding data eeprom information in the hex file, it should start at address, f00000h. microchip technology inc. believes that this feature is important for the benefit of the end customer. 5.5 checksum computation the checksum is calculated by summing the following: ? the contents of all code memory locations ? the configuration word, appropriately masked ? id locations. the least significant 16 bits of this sum are the checksum. table 5-4 (starting on page 41 ) describes how to calculate the checksum for each device. for these examples, the id memory has been set to ?use unpro- tected checksum? in mplab ide ? . please use this value to determine the value of the ?sum(ids)? term for each appropriate code-protected example. note: the checksum calculation differs depend- ing on the code-protect setting. since the code memory locations read out differently depending on the code-protect setting, the table describes how to manipulate the actual code memory values to simulate the values that would be read from a protected device. when calculating a checksum by reading a device, the entire code memory can simply be read and summed. the configuration word and id locations can always be read. ? 2011 microchip technology inc. ds39972b-page 41 pic18fxxk80 family table 5-4: checksum computation device code-protect checksum blank value 0xaa at 0 and max address pic18f66k80 none sum(0000:0fff) + sum(1000:3fff) + sum(4000:7fff) + sum(8000:bfff) + sum(c000:ffff) + (config1l=5d & 5d) + (config1h=08 & df) + (config2l=7f & 7f) + (config2h=7f & 7f) + (config3l=00 & 00) + (config3h=8f & 8f) + (config4l= 91 & 91) + (config4h=00 & 00) + (config5l=0f & 0f) + (config5h=c0 & c0) + (config6l=0f & 0f) + (config6h=e0 & e0) + (config7l=0f & 0f) + (config7h=40 & 40) 0x0490 0x03e6 boot block 2k word sum(1000:3fff) + sum(4000:7fff) + sum(8000:bfff) + sum(c000:ffff) + (config1l=5d & 5d) + (config1h=08 & df) + (config2l=7f & 7f) + (config2h=7f & 7f) + (config3l=00 & 00) + (config3h=8f & 8f) + (config4l=91 & 91) + (config4h=00 & 00) + (config5l=0f & 0f) + (config5h=80 & c0) + (config6l=0f & 0f) + (config6h=e0 & e0) + (config7l=0f & 0f) + (con fig7h=40 & 40) + sum(ids) 0x145d 0x1412 boot/panel0/ panel1 sum(8000:bfff) + sum(c000:ffff) + (config1l=5d & 5d) + (config1h=08 & df) + (config2l=7f & 7f) + (config2h=7f & 7f) + (config3l=00 & 00) + (config3h=8f & 8f) + (config4l=91 & 91) + (config4h=00 & 00) + (config5l=0c & 0f) + (config5h=80 & c0) + (config6l=0f & 0f) + (config6h=e0 & e0) + (config7l=0f & 0f) + (config7h=40 & 40) + sum(ids) 0x845a 0x840f all (config1l=5d & 5d) + (config1h=08 & df) + (config2l=7f & 7f) + (config2h=7f & 7f) + (config3l=00 & 00) + (config3h=8f & 8f) + (config4l=91 & 91) + (config4h=00 & 00) + (config5l=00 & 0f) + (config5h=80 & c0) + (config6l=0f & 0f) + (config6h=e0 & e0) + (config7l=0f & 0f) + (con fig7h=40 & 40) + sum(ids) 0x044e 0x0458 pic18f65k80 none sum(0000:0 fff) + sum(1000:1fff) + sum(2000:3fff) + sum(4000:5fff) + sum(6000:7fff) + (config1l=5d & 5d) + (config1h=08 & df) + (config2l=7f & 7f) + (config2h=7f & 7f) + (config3l=00 & 00) + (config3h=8f & 8f) + (config4l=91 & 91) + (config4h=00 & 00) + (config5l=0f & 0f) + (config5h=c0 & c0) + (config6l=0f & 0f) + (config6h=e0 & e0) + (config7l=0f & 0f) + (config7h=40 & 40) 0x8490 0x83e6 boot block 2k word sum(1000:1fff) + sum(2000:3fff) + sum(4000:5fff) + sum(6000:7fff) + (config1l=5d & 5d) + (config1h=08 & df) + (config2l=7f & 7f) + (config2h=7f & 7f) + (config3l=00 & 00) + (config3h=8f & 8f) + (config4l=91 & 91) + (config4h=00 & 00) + (config5l=0f & 0f) + (config5h=80 & c0) + (config6l=0f & 0f) + (config6h=e0 & e0) + (config7l=0f & 0f) + (con fig7h=40 & 40) + sum(ids) 0x9465 0x941a boot/panel0/ panel1 sum(4000:5fff) + sum(6000:7fff) + (config1l=5d & 5d) + (config1h=08 & df) + (config2l=7f & 7f) + (config2h=7f & 7f) + (config3l=00 & 00) + (config3h=8f & 8f) + (config4l=91 & 91) + (config4h=00 & 00) + (config5l=0c & 0f) + (config5h=80 & c0) + (config6l=0f & 0f) + (config6h=e0 & e0) + (config7l=0f & 0f) + (config7h=40 & 40) + sum(ids) 0xc462 0xc417 all (config1l=5d & 5d) + (config1h=08 & df) + (config2l=7f & 7f) + (config2h=7f & 7f) + (config3l=00 & 00) + (config3h=8f & 8f) + (config4l=91 & 91) + (config4h=00 & 00) + (config5l=00 & 0f) + (config5h=80 & c0) + (config6l=0f & 0f) + (config6h=e0 & e0) + (config7l=0f & 0f) + (con fig7h=40 & 40) + sum(ids) 0x0456 0x0460 pic18fxxk80 family ds39972b-page 42 ? 2011 microchip technology inc. pic18f46k80 none sum(0000:0fff) + sum(1000:3fff) + sum(4000:7fff) + sum(8000:bfff) + sum(c000:ffff) + (config1l=5d & 5d) + (config1h=08 & df) + (config2l=7f & 7f) + (config2h=7f & 7f) + (config3l=00 & 00) + (config3h=89 & 89) + (config4l=91 & 91) + (config4h=00 & 00) + (config5l=0f & 0f) + (config5h=c0 & c0) + (config6l=0f & 0f) + (config6h=e0 & e0) + (config7l=0f & 0f) + (config7h=40 & 40) 0x048a 0x03e0 boot block 2k word sum(1000:3fff) + sum(4000:7fff) + sum(8000:bfff) + sum(c000:ffff) + (config1l=5d & 5d) + (config1h=08 & df) + (config2l=7f & 7f) + (config2h=7f & 7f) + (config3l=00 & 00) + (config3h=89 & 89) + (config4l=91 & 91) + (config4h=00 & 00) + (config5l=0f & 0f) + (config5h=80 & c0) + (config6l=0f & 0f) + (config6h=e0 & e0) + (config7l=0f & 0f) + (config7h=40 & 40) + sum(ids) 0x1460 0x1406 boot/panel0/ panel1 sum(8000:bfff) + sum(c000:ffff) + (config1l=5d & 5d) + (config1h=08 & df) + (config2l=7f & 7f) + (config2h=7f & 7f) + (config3l=00 & 00) + (config3h=89 & 89) + (config4l=91 & 91) + (config4h=00 & 00) + (config5l=0c & 0f) + (config5h=80 & c0) + (config6l=0f & 0f) + (config6h=e0 & e0) + (config7l=0f & 0f) + (config7h=40 & 40) + sum(ids) 0x845d 0x8403 all (config1l=5d & 5d) + (config1h=08 & df) + (config2l=7f & 7f) + (config2h=7f & 7f) + (config3l=00 & 00) + (config3h=89 & 89) + (config4l=91 & 91) + (config4h=00 & 00) + (config5l=00 & 0f) + (config5h=80 & c0) + (config6l=0f & 0f) + (config6h=e0 & e0) + (config7l=0f & 0f) + (config7h=40 & 40) + sum(ids) 0x0451 0x044c pic18f45k80 none sum(0000:0fff) + sum(1000:1fff) + sum(2000:3fff) + sum(4000:5fff) + sum(6000:7fff) + (config1l=5d & 5d) + (config1h=08 & df) + (config2l=7f & 7f) + (config2h=7f & 7f) + (config3l=00 & 00) + (config3h=89 & 89) + (config4l=91 & 91) + (config4h=00 & 00) + (config5l=0f & 0f) + (config5h=c0 & c0) + (config6l=0f & 0f) + (config6h=e0 & e0) + (config7l=0f & 0f) + (config7h=40 & 40) 0x848a 0x83e0 boot block 2k word sum(1000:1fff) + sum(2000:3fff) + sum(4000:5fff) + sum(6000:7fff) + (config1l=5d & 5d) + (config1h=08 & df) + (config2l=7f & 7f) + (config2h=7f & 7f) + (config3l=00 & 00) + (config3h=89 & 89) + (config4l=91 & 91) + (config4h=00 & 00) + (config5l=0f & 0f) + (config5h=80 & c0) + (config6l=0f & 0f) + (config6h=e0 & e0) + (config7l=0f & 0f) + (config7h=40 & 40) + sum(ids) 0x9468 0x940e boot/panel0/ panel1 sum(4000:5fff) + sum(6000:7fff) + (confi g1l=5d & 5d) + (config1h=08 & df) + (config2l=7f & 7f) + (config2h= 7f & 7f) + (config3l=00 & 00) + (config3h=89 & 89) + (config4l=91 & 91) + (config4h=00 & 00) + (config5l=0c & 0f) + (config5h=80 & c0) + (config6l=0f & 0f) + (config6h=e0 & e0) + (config7l=0f & 0f) + (config7h=40 & 40) + sum(ids) 0xc465 0xc40b all (config1l=5d & 5d) + (config1h= 08 & df) + (config2l=7f & 7f) + (config2h=7f & 7f) + (config3l=00 & 00) + (config3h=89 & 89) + (config4l=91 & 91) + (config4h=00 & 00) + (config5l=00 & 0f) + (config5h=80 & c0) + (config6l=0f & 0f) + (config6h=e0 & e0) + (config7l=0f & 0f) + (config7h=40 & 40) + sum(ids) 0x0459 0x0454 table 5-4: checksum computation (continued) device code-protect checksum blank value 0xaa at 0 and max address ? 2011 microchip technology inc. ds39972b-page 43 pic18fxxk80 family pic18f26k80 none sum(0000:0fff) + sum(1000:3fff) + sum(4000:7fff) + sum(8000:bfff) + sum(c000:ffff) + (config1l=5d & 5d) + (config1h=08 & df) + (config2l=7f & 7f) + (config2h=7f & 7f) + (config3l=00 & 00) + (config3h=89 & 89) + (config4l=91 & 91) + (config4h=00 & 00) + (config5l=0f & 0f) + (config5h=c0 & c0) + (config6l=0f & 0f) + (config6h=e0 & e0) + (config7l=0f & 0f) + (config7h=40 & 40) 0x048a 0x03e0 boot block 2k word sum(1000:3fff) + sum(4000:7fff) + sum(8000:bfff) + sum(c000:ffff) + (config1l=5d & 5d) + (config1h=08 & df) + (config2l=7f & 7f) + (config2h=7f & 7f) + (config3l=00 & 00) + (config3h=89 & 89) + (config4l=91 & 91) + (config4h=00 & 00) + (config5l=0f & 0f) + (config5h=80 & c0) + (config6l=0f & 0f) + (config6h=e0 & e0) + (config7l=0f & 0f) + (config7h=40 & 40) + sum(ids) 0x1460 0x1406 boot/panel0/ panel1 sum(8000:bfff) + sum(c000:ffff) + (config1l=5d & 5d) + (config1h=08 & df) + (config2l=7f & 7f) + (config2h=7f & 7f) + (config3l=00 & 00) + (config3h=89 & 89) + (config4l=91 & 91) + (config4h=00 & 00) + (config5l=0c & 0f) + (config5h=80 & c0) + (config6l=0f & 0f) + (config6h=e0 & e0) + (config7l=0f & 0f) + (config7h=40 & 40) + sum(ids) 0x845d 0x8403 all (config1l=5d & 5d) + (config1h=08 & df) + (config2l=7f & 7f) + (config2h=7f & 7f) + (config3l=00 & 00) + (config3h=89 & 89) + (config4l=91 & 91) + (config4h=00 & 00) + (config5l=00 & 0f) + (config5h=80 & c0) + (config6l=0f & 0f) + (config6h=e0 & e0) + (config7l=0f & 0f) + (config7h=40 & 40) + sum(ids) 0x0451 0x044c pic18f25k80 none sum(0000:0fff) + sum(1000:1fff) + sum(2000:3fff) + sum(4000:5fff) + sum(6000:7fff) + (config1l=5d & 5d) + (config1h=08 & df) + (config2l=7f & 7f) + (config2h=7f & 7f) + (config3l=00 & 00) + (config3h=89 & 89) + (config4l=91 & 91) + (config4h=00 & 00) + (config5l=0f & 0f) + (config5h=c0 & c0) + (config6l=0f & 0f) + (config6h=e0 & e0) + (config7l=0f & 0f) + (config7h=40 & 40) 0x848a 0x83e0 boot block 2k word sum(1000:1fff) + sum(2000:3fff) + sum(4000:5fff) + sum(6000:7fff) + (config1l=5d & 5d) + (config1h=08 & df) + (config2l=7f & 7f) + (config2h=7f & 7f) + (config3l=00 & 00) + (config3h=89 & 89) + (config4l=91 & 91) + (config4h=00 & 00) + (config5l=0f & 0f) + (config5h=80 & c0) + (config6l=0f & 0f) + (config6h=e0 & e0) + (config7l=0f & 0f) + (config7h=40 & 40) + sum(ids) 0x9468 0x940e boot/panel0/ panel1 sum(4000:5fff) + sum(6000:7fff) + (config1l=5d & 5d) + (config1h=08 & df) + (config2l=7f & 7f) + (config2h=7f & 7f) + (config3l=00 & 00) + (config3h=89 & 89) + (config4l=91 & 91) + (config4h=00 & 00) + (config5l=0c & 0f) + (config5h=80 & c0) + (config6l=0f & 0f) + (config6h=e0 & e0) + (config7l=0f & 0f) + (config7h=40 & 40) + sum(ids) 0xc465 0xc40b all (config1l=5d & 5d) + (config1h=08 & df) + (config2l=7f & 7f) + (config2h=7f & 7f) + (config3l=00 & 00) + (config3h=89 & 89) + (config4l=91 & 91) + (config4h=00 & 00) + (config5l=00 & 0f) + (config5h=80 & c0) + (config6l=0f & 0f) + (config6h=e0 & e0) + (config7l=0f & 0f) + (config7h=40 & 40) + sum(ids) 0x0459 0x0454 table 5-4: checksum computation (continued) device code-protect checksum blank value 0xaa at 0 and max address pic18fxxk80 family ds39972b-page 44 ? 2011 microchip technology inc. pic18lf66k80 none sum(0000:0fff) + sum(1000:3fff) + sum(4000:7fff) + sum(8000:bfff) + sum(c000:ffff) + (config1l=5d & 5d) + (config1h=08 & df) + (config2l=7f & 7f) + (config2h=7f & 7f) + (config3l=00 & 00) + (config3h=8f & 8f) + (config4l=91 & 91) + (config4h=00 & 00) + (config5l=0f & 0f) + (config5h=c0 & c0) + (config6l=0f & 0f) + (config6h=e0 & e0) + (config7l=0f & 0f) + (config7h=40 & 40) 0x0490 0x03e6 boot block 2k word sum(1000:3fff) + sum(4000:7fff) + sum(8000:bfff) + sum(c000:ffff) + (config1l=5d & 5d) + (config1h=08 & df) + (config2l=7f & 7f) + (config2h=7f & 7f) + (config3l=00 & 00) + (config3h=8f & 8f) + (config4l=91 & 91) + (config4h=00 & 00) + (config5l=0f & 0f) + (config5h=80 & c0) + (config6l=0f & 0f) + (config6h=e0 & e0) + (config7l=0f & 0f) + (config7h=40 & 40) + sum(ids) 0x145d 0x1412 boot/panel0/ panel1 sum(8000:bfff) + sum(c000:ffff) + (config1l=5d & 5d) + (config1h=08 & df) + (config2l=7f & 7f) + (config2h=7f & 7f) + (config3l=00 & 00) + (config3h=8f & 8f) + (config4l=91 & 91) + (config4h=00 & 00) + (config5l=0c & 0f) + (config5h=80 & c0) + (config6l=0f & 0f) + (config6h=e0 & e0) + (config7l=0f & 0f) + (config7h=40 & 40) + sum(ids) 0x845a 0x840f all (config1l=5d & 5d) + (config1h=08 & df) + (config2l=7f & 7f) + (config2h=7f & 7f) + (config3l=00 & 00) + (config3h=8f & 8f) + (config4l=91 & 91) + (config4h=00 & 00) + (config5l=00 & 0f) + (config5h=80 & c0) + (config6l=0f & 0f) + (config6h=e0 & e0) + (config7l=0f & 0f) + (config7h=40 & 40) + sum(ids) 0x044e 0x0458 PIC18LF65K80 none sum(0000:0 fff) + sum(1000:1fff) + sum(2000:3fff) + sum(4000:5fff) + sum(6000:7fff) + (config1l=5d & 5d) + (config1h=08 & df) + (config2l=7f & 7f) + (config2h=7f & 7f) + (config3l=00 & 00) + (config3h=8f & 8f) + (config4l=91 & 91) + (config4h=00 & 00) + (config5l=0f & 0f) + (config5h=c0 & c0) + (config6l=0f & 0f) + (config6h=e0 & e0) + (config7l=0f & 0f) + (config7h=40 & 40) 0x8490 0x83e6 boot block 2k word sum(1000:1fff) + sum(2000:3fff) + sum(4000:5fff) + sum(6000:7fff) + (config1l=5d & 5d) + (config1h=08 & df) + (config2l=7f & 7f) + (config2h=7f & 7f) + (config3l=00 & 00) + (config3h=8f & 8f) + (config4l=91 & 91) + (config4h=00 & 00) + (config5l=0f & 0f) + (config5h=80 & c0) + (config6l=0f & 0f) + (config6h=e0 & e0) + (config7l=0f & 0f) + (config7h=40 & 40) + sum(ids) 0x9465 0x941a boot/panel0/ panel1 sum(4000:5fff) + sum(6000:7fff) + (config1l=5d & 5d) + (config1h=08 & df) + (config2l=7f & 7f) + (config2h=7f & 7f) + (config3l=00 & 00) + (config3h=8f & 8f) + (config4l=91 & 91) + (config4h=00 & 00) + (config5l=0c & 0f) + (config5h=80 & c0) + (config6l=0f & 0f) + (config6h=e0 & e0) + (config7l=0f & 0f) + (config7h=40 & 40) + sum(ids) 0xc462 0xc417 all (config1l=5d & 5d) + (config1h=08 & df) + (config2l=7f & 7f) + (config2h=7f & 7f) + (config3l=00 & 00) + (config3h=8f & 8f) + (config4l=91 & 91) + (config4h=00 & 00) + (config5l=00 & 0f) + (config5h=80 & c0) + (config6l=0f & 0f) + (config6h=e0 & e0) + (config7l=0f & 0f) + (config7h=40 & 40) + sum(ids) 0x0456 0x0460 table 5-4: checksum computation (continued) device code-protect checksum blank value 0xaa at 0 and max address ? 2011 microchip technology inc. ds39972b-page 45 pic18fxxk80 family pic18lf46k80 none sum(0000:0fff) + sum(1000:3fff) + sum(4000:7fff) + sum(8000:bfff) + sum(c000:ffff) + (config1l=5d & 5d) + (config1h=08 & df) + (config2l=7f & 7f) + (config2h=7f & 7f) + (config3l=00 & 00) + (config3h=89 & 89) + (config4l=91 & 91) + (config4h=00 & 00) + (config5l=0f & 0f) + (config5h=c0 & c0) + (config6l=0f & 0f) + (config6h=e0 & e0) + (config7l=0f & 0f) + (config7h=40 & 40) 0x048a 0x03e0 boot block 2k word sum(1000:3fff) + sum(4000:7fff) + sum(8000:bfff) + sum(c000:ffff) + (config1l=5d & 5d) + (config1h=08 & df) + (config2l=7f & 7f) + (config2h=7f & 7f) + (config3l=00 & 00) + (config3h=89 & 89) + (config4l=91 & 91) + (config4h=00 & 00) + (config5l=0f & 0f) + (config5h=80 & c0) + (config6l=0f & 0f) + (config6h=e0 & e0) + (config7l=0f & 0f) + (config7h=40 & 40) + sum(ids) 0x1460 0x1406 boot/panel0/ panel1 sum(8000:bfff) + sum(c000:ffff) + (config1l=5d & 5d) + (config1h=08 & df) + (config2l=7f & 7f) + (config2h=7f & 7f) + (config3l=00 & 00) + (config3h=89 & 89) + (config4l=91 & 91) + (config4h=00 & 00) + (config5l=0c & 0f) + (config5h=80 & c0) + (config6l=0f & 0f) + (config6h=e0 & e0) + (config7l=0f & 0f) + (config7h=40 & 40) + sum(ids) 0x845d 0x8403 all (config1l=5d & 5d) + (config1h=08 & df) + (config2l=7f & 7f) + (config2h=7f & 7f) + (config3l=00 & 00) + (config3h=89 & 89) + (config4l=91 & 91) + (config4h=00 & 00) + (config5l=00 & 0f) + (config5h=80 & c0) + (config6l=0f & 0f) + (config6h=e0 & e0) + (config7l=0f & 0f) + (config7h=40 & 40) + sum(ids) 0x0451 0x044c pic18lf45k80 none sum(0000:0fff) + sum(1000:1fff) + sum(2000:3fff) + sum(4000:5fff) + sum(6000:7fff) + (config1l=5d & 5d) + (config1h=08 & df) + (config2l=7f & 7f) + (config2h=7f & 7f) + (config3l=00 & 00) + (config3h=89 & 89) + (config4l=91 & 91) + (config4h=00 & 00) + (config5l=0f & 0f) + (config5h=c0 & c0) + (config6l=0f & 0f) + (config6h=e0 & e0) + (config7l=0f & 0f) + (config7h=40 & 40) 0x848a 0x83e0 boot block 2k word sum(1000:1fff) + sum(2000:3fff) + sum(4000:5fff) + sum(6000:7fff) + (config1l=5d & 5d) + (config1h=08 & df) + (config2l=7f & 7f) + (config2h=7f & 7f) + (config3l=00 & 00) + (config3h=89 & 89) + (config4l=91 & 91) + (config4h=00 & 00) + (config5l=0f & 0f) + (config5h=80 & c0) + (config6l=0f & 0f) + (config6h=e0 & e0) + (config7l=0f & 0f) + (config7h=40 & 40) + sum(ids) 0x9468 0x940e boot/panel0/ panel1 sum(4000:5fff) + sum(6000:7fff) + (config1l=5d & 5d) + (config1h=08 & df) + (config2l=7f & 7f) + (config2h=7f & 7f) + (config3l=00 & 00) + (config3h=89 & 89) + (config4l=91 & 91) + (config4h=00 & 00) + (config5l=0c & 0f) + (config5h=80 & c0) + (config6l=0f & 0f) + (config6h=e0 & e0) + (config7l=0f & 0f) + (config7h=40 & 40) + sum(ids) 0xc465 0xc40b all (config1l=5d & 5d) + (config1h=08 & df) + (config2l=7f & 7f) + (config2h=7f & 7f) + (config3l=00 & 00) + (config3h=89 & 89) + (config4l=91 & 91) + (config4h=00 & 00) + (config5l=00 & 0f) + (config5h=80 & c0) + (config6l=0f & 0f) + (config6h=e0 & e0) + (config7l=0f & 0f) + (config7h=40 & 40) + sum(ids) 0x0459 0x0454 table 5-4: checksum computation (continued) device code-protect checksum blank value 0xaa at 0 and max address pic18fxxk80 family ds39972b-page 46 ? 2011 microchip technology inc. pic18lf26k80 none sum(0000:0fff) + sum(1000:3fff) + sum(4000:7fff) + sum(8000:bfff) + sum(c000:ffff) + (config1l=5d & 5d) + (config1h=08 & df) + (config2l=7f & 7f) + (config2h=7f & 7f) + (config3l=00 & 00) + (config3h=89 & 89) + (config4l=91 & 91) + (config4h=00 & 00) + (config5l=0f & 0f) + (config5h=c0 & c0) + (config6l=0f & 0f) + (config6h=e0 & e0) + (config7l=0f & 0f) + (config7h=40 & 40) 0x048a 0x03e0 boot block 2k word sum(1000:3fff) + sum(4000:7fff) + sum(8000:bfff) + sum(c000:ffff) + (config1l=5d & 5d) + (config1h=08 & df) + (config2l=7f & 7f) + (config2h=7f & 7f) + (config3l=00 & 00) + (config3h=89 & 89) + (config4l=91 & 91) + (config4h=00 & 00) + (config5l=0f & 0f) + (config5h=80 & c0) + (config6l=0f & 0f) + (config6h=e0 & e0) + (config7l=0f & 0f) + (config7h=40 & 40) + sum(ids) 0x1460 0x1406 boot/panel0/ panel1 sum(8000:bfff) + sum(c000:ffff) + (config1l=5d & 5d) + (config1h=08 & df) + (config2l=7f & 7f) + (config2h=7f & 7f) + (config3l=00 & 00) + (config3h=89 & 89) + (config4l=91 & 91) + (config4h=00 & 00) + (config5l=0c & 0f) + (config5h=80 & c0) + (config6l=0f & 0f) + (config6h=e0 & e0) + (config7l=0f & 0f) + (config7h=40 & 40) + sum(ids) 0x845d 0x8403 all (config1l=5d & 5d) + (config1h=08 & df) + (config2l=7f & 7f) + (config2h=7f & 7f) + (config3l=00 & 00) + (config3h=89 & 89) + (config4l=91 & 91) + (config4h=00 & 00) + (config5l=00 & 0f) + (config5h=80 & c0) + (config6l=0f & 0f) + (config6h=e0 & e0) + (config7l=0f & 0f) + (config7h=40 & 40) + sum(ids) 0x0451 0x044c pic18lf25k80 none sum(0000:0fff) + sum(1000:1fff) + sum(2000:3fff) + sum(4000:5fff) + sum(6000:7fff) + (config1l=5d & 5d) + (config1h=08 & df) + (config2l=7f & 7f) + (config2h=7f & 7f) + (config3l=00 & 00) + (config3h=89 & 89) + (config4l=91 & 91) + (config4h=00 & 00) + (config5l=0f & 0f) + (config5h=c0 & c0) + (config6l=0f & 0f) + (config6h=e0 & e0) + (config7l=0f & 0f) + (config7h=40 & 40) 0x848a 0x83e0 boot block 2k word sum(1000:1fff) + sum(2000:3fff) + sum(4000:5fff) + sum(6000:7fff) + (config1l=5d & 5d) + (config1h=08 & df) + (config2l=7f & 7f) + (config2h=7f & 7f) + (config3l=00 & 00) + (config3h=89 & 89) + (config4l=91 & 91) + (config4h=00 & 00) + (config5l=0f & 0f) + (config5h=80 & c0) + (config6l=0f & 0f) + (config6h=e0 & e0) + (config7l=0f & 0f) + (config7h=40 & 40) + sum(ids) 0x9468 0x940e boot/panel0/ panel1 sum(4000:5fff) + sum(6000:7fff) + (config1l=5d & 5d) + (config1h=08 & df) + (config2l=7f & 7f) + (config2h=7f & 7f) + (config3l=00 & 00) + (config3h=89 & 89) + (config4l=91 & 91) + (config4h=00 & 00) + (config5l=0c & 0f) + (config5h=80 & c0) + (config6l=0f & 0f) + (config6h=e0 & e0) + (config7l=0f & 0f) + (config7h=40 & 40) + sum(ids) 0xc465 0xc40b all (config1l=5d & 5d) + (config1h=08 & df) + (config2l=7f & 7f) + (config2h=7f & 7f) + (config3l=00 & 00) + (config3h=89 & 89) + (config4l=91 & 91) + (config4h=00 & 00) + (config5l=00 & 0f) + (config5h=80 & c0) + (config6l=0f & 0f) + (config6h=e0 & e0) + (config7l=0f & 0f) + (config7h=40 & 40) + sum(ids) 0x0459 0x0454 table 5-4: checksum computation (continued) device code-protect checksum blank value 0xaa at 0 and max address ? 2011 microchip technology inc. ds39972b-page 47 pic18fxxk80 family 6.0 ac/dc characteristics timing requirements for program/verify test mode standard operating conditions operating temperature: 25 ? c is recommended param no. sym characteristic min max units conditions d110 v ihh high-voltage programming voltage on mclr /v pp /re3 v dd + 1.5 9 v d111 v dd supply voltage during programming 2.1 5.5 v row erase/write for ?f? parts 2.7 5.5 v block erase operations for ?f? parts 2.1 3.6 v row erase/write for ?lf? parts 2.7 3.6 v block erase operations for ?lf? parts d112 i pp programming current on mclr /v pp /re3 ? 600 ? a d113 i ddp supply current during programming ? 3.0 ma d031 v il input low voltage v ss 0.2 v dd v d041 v ih input high voltage 0.8 v dd v dd v d080 v ol output low voltage ? 0.6 v i ol = 8.5 ma @ 4.5v d090 v oh output high voltage v dd ? 0.7 ? v i oh = -3.0 ma @ 4.5v d012 c io capacitive loading on i/o pin (pgd) ? 50 pf to meet ac specifications p1 t r mclr /v pp /re3 rise time to enter program/verify mode ?1.0 ? s (note 1) p2 t pgc serial clock (pgc) period 100 ? ns v dd = 5.0v 1? ? sv dd = 2.0v p2a t pgcl serial clock (pgc) low time 40 ? ns v dd = 5.0v 400 ? ns v dd = 2.0v p2b t pgch serial clock (pgc) high time 40 ? ns v dd = 5.0v 400 ? ns v dd = 2.0v p3 t set 1 input data setup time to serial clock ? 15 ? ns p4 t hld 1 input data hold time from pgc ?? 15 ? ns p5 t dly 1 delay between 4-bit command and command operand 40 ? ns p5a t dly 1 a delay between 4-bit command operand and next 4-bit command 40 ? ns p6 t dly 2 delay between last pgc ? of command byte to first pgc ? of read of data word 20 ? ns p9 t dly 5 pgc high time (minimum programming time) 1 ? ms externally timed p9a t dly 5a pgc high time 5 ? ms configuration word programming time p10 t dly 6 pgc low time after programming (high-voltage discharge time) 100 ? ? s note 1: do not allow excess time when transitioning mclr between v il and v ihh ; this can cause spurious program executions to occur. the maximum transition time is: 1 t cy + t pwrt (if enabled) + 1024 t osc (for lp, hs, hs/pll and xt modes only) + 2 ms (for hs/pll mode only) + 1.5 ? s (for ec mode only) where t cy is the instruction cycle time, t pwrt is the power-up timer period and t osc is the oscillator period. for specific values, refer to the electrical characteristics section of the device data sheet for the particular device. pic18fxxk80 family ds39972b-page 48 ? 2011 microchip technology inc. p11 t dly 7 delay to allow self-timed data write or block erase to occur 5?ms p11a t drwt data write polling time 4 ? ms p12 t hld 2 input data hold time from mclr /v pp /re3 ? 250 ? ? s p13 t set 2v dd ?? setup time to mclr /v pp /re3 ? 100 ? ns p14 t valid data out valid from pgc ? 10 ? ns p15 t dly 8 delay between last pgc ? and mclr /v pp /re3 ? 0?s p16 t hld 3mclr /v pp /re3 ?? to v dd ? ?100ns p17 t hld 3mclr /v pp /re3 ?? to v dd ?? ?100ns 6.0 ac/dc characteristics timing requirements for program/verify test mode (continued) standard operating conditions operating temperature: 25 ? c is recommended param no. sym characteristic min max units conditions note 1: do not allow excess time when transitioning mclr between v il and v ihh ; this can cause spurious program executions to occur. the maximum transition time is: 1 t cy + t pwrt (if enabled) + 1024 t osc (for lp, hs, hs/pll and xt modes only) + 2 ms (for hs/pll mode only) + 1.5 ? s (for ec mode only) where t cy is the instruction cycle time, t pwrt is the power-up timer period and t osc is the oscillator period. for specific values, refer to the electrical characteristics section of the device data sheet for the particular device. ? 2011 microchip technology inc. ds39972b-page 49 pic18fxxk80 family appendix a: revision history revision a (march 2010) original programming specification for the pic18fxxk80 family devices. revision b (january 2011) updated section 2.3 ?on-chip voltage regulator? with correct capacitor information. updated table 5-4 and section 6.0 ?ac/dc characteristics timing requirements for program/verify test mode? . minor grammatical corrections made throughout text. pic18fxxk80 family ds39972b-page 50 ? 2011 microchip technology inc. notes: ? 2011 microchip technology inc. ds39972b-page 51 information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, dspic, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, pic 32 logo, rfpic and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. filterlab, hampshire, hi-tech c, linear active thermistor, mxdev, mxlab, seeval and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, appl ication maestro, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, hi-tide, in-circuit serial programming, icsp, mindi, miwi, mpasm, mplab certified logo, mplib, mplink, mtouch, omniscient code generation, picc, picc-18, picdem, picdem.net, pickit, pictail, real ice, rflab, select mode, total endurance, tsharc, uniwindriver, wiperlock and zena are trademarks of microchip tec hnology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2011, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. isbn: 978-1-60932-837-5 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchip?s code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. ds39972b-page 52 ? 2011 microchip technology inc. americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: http://support.microchip.com web address: www.microchip.com atlanta duluth, ga tel: 678-957-9614 fax: 678-957-1455 boston westborough, ma tel: 774-760-0087 fax: 774-760-0088 chicago itasca, il tel: 630-285-0071 fax: 630-285-0075 cleveland independence, oh tel: 216-447-0464 fax: 216-447-0643 dallas addison, tx tel: 972-818-7423 fax: 972-818-2924 detroit farmington hills, mi tel: 248-538-2250 fax: 248-538-2260 kokomo kokomo, in tel: 765-864-8360 fax: 765-864-8387 los angeles mission viejo, ca tel: 949-462-9523 fax: 949-462-9608 santa clara santa clara, ca tel: 408-961-6444 fax: 408-961-6445 toronto mississauga, ontario, canada tel: 905-673-0699 fax: 905-673-6509 asia/pacific asia pacific office suites 3707-14, 37th floor tower 6, the gateway harbour city, kowloon hong kong tel: 852-2401-1200 fax: 852-2401-3431 australia - sydney tel: 61-2-9868-6733 fax: 61-2-9868-6755 china - beijing tel: 86-10-8528-2100 fax: 86-10-8528-2104 china - chengdu tel: 86-28-8665-5511 fax: 86-28-8665-7889 china - chongqing tel: 86-23-8980-9588 fax: 86-23-8980-9500 china - hong kong sar tel: 852-2401-1200 fax: 852-2401-3431 china - nanjing tel: 86-25-8473-2460 fax: 86-25-8473-2470 china - qingdao tel: 86-532-8502-7355 fax: 86-532-8502-7205 china - shanghai tel: 86-21-5407-5533 fax: 86-21-5407-5066 china - shenyang tel: 86-24-2334-2829 fax: 86-24-2334-2393 china - shenzhen tel: 86-755-8203-2660 fax: 86-755-8203-1760 china - wuhan tel: 86-27-5980-5300 fax: 86-27-5980-5118 china - xian tel: 86-29-8833-7252 fax: 86-29-8833-7256 china - xiamen tel: 86-592-2388138 fax: 86-592-2388130 china - zhuhai tel: 86-756-3210040 fax: 86-756-3210049 asia/pacific india - bangalore tel: 91-80-3090-4444 fax: 91-80-3090-4123 india - new delhi tel: 91-11-4160-8631 fax: 91-11-4160-8632 india - pune tel: 91-20-2566-1512 fax: 91-20-2566-1513 japan - yokohama tel: 81-45-471- 6166 fax: 81-45-471-6122 korea - daegu tel: 82-53-744-4301 fax: 82-53-744-4302 korea - seoul tel: 82-2-554-7200 fax: 82-2-558-5932 or 82-2-558-5934 malaysia - kuala lumpur tel: 60-3-6201-9857 fax: 60-3-6201-9859 malaysia - penang tel: 60-4-227-8870 fax: 60-4-227-4068 philippines - manila tel: 63-2-634-9065 fax: 63-2-634-9069 singapore tel: 65-6334-8870 fax: 65-6334-8850 taiwan - hsin chu tel: 886-3-6578-300 fax: 886-3-6578-370 taiwan - kaohsiung tel: 886-7-213-7830 fax: 886-7-330-9305 taiwan - taipei tel: 886-2-2500-6610 fax: 886-2-2508-0102 thailand - bangkok tel: 66-2-694-1351 fax: 66-2-694-1350 europe austria - wels tel: 43-7242-2244-39 fax: 43-7242-2244-393 denmark - copenhagen tel: 45-4450-2828 fax: 45-4485-2829 france - paris tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany - munich tel: 49-89-627-144-0 fax: 49-89-627-144-44 italy - milan tel: 39-0331-742611 fax: 39-0331-466781 netherlands - drunen tel: 31-416-690399 fax: 31-416-690340 spain - madrid tel: 34-91-708-08-90 fax: 34-91-708-08-91 uk - wokingham tel: 44-118-921-5869 fax: 44-118-921-5820 worldwide sales and service 08/04/10 |
Price & Availability of PIC18LF65K80
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |